As DRAM's increase in memory cell density, it becomes increasingly difficult to make electrical contact to diffusion regions which are formed in the underlying substrate.
Conventional stacked capacitor DRAM arrays utilize either a buried bit line or non-buried bit line construction. With buried bit line constructions, bit lines are provided in close vertical proximity to the bit line contacts of the memory cell field effect transistor (FET's) with the cell capacitors being formed horizontally over the top of the word lines and bit lines. With non-buried bit line constructions, deep vertical contacts are made through a thick insulating layer to the cell FET's, with a capacitor construction being provided over the word lines and beneath the bit lines. Such non-buried bit line constructions are also referred to as "capacitor-under bit line" or "bit line over capacitor constructions".
In the fabrication of word lines and gates for field effect transistors, the word lines or gates are typically encapsulated or surrounded by a nitride or oxide insulating material. During fabrication, and subsequent to the provision of the nitride or oxide insulating material, an insulating layer such as BPSG is provided outwardly of the gate and over the substrate in adjacent diffusion regions. In view of the increase in memory cell density of DRAM arrays, fabricators of such devices have found it increasingly difficult to selectively remove the BPSG layer, as by etching, relative to both the nitride or oxide layers while simultaneously avoiding the removal of the underlying substrate.
In view of this perceived difficulty, fabricators of such devices have employed, heretofore, a thin, intervening etch stop layer which is disposed in covering relation relative to the word lines, gates and adjacent substrate areas. Such an intervening etch stop layer normally comprises a thin nitride layer. In the practice of the prior art, an etching chemistry is employed which selectively removes the BPSG layer relative to the nitride layer. Thereafter, the nitride is selectively removed relative to the underlying substrate and oxide thus effectively outwardly exposing the diffusion region of the substrate. The resulting contact opening provided by such selective removal is thereafter filled with conductive material which makes electrical contact to the underlying diffusion region.
A method of forming CMOS and other circuitry which avoids the shortcomings of the prior art is the subject matter of the present invention.